1. Field of the Invention
The present invention relates, in general, to a method for fabricating a capacitor of semiconductor memory device and, more particularly, to improvement in the electrostatic capacity of cell along with the method.
2. Description of the Prior Art
As semiconductor industry grows, the development of memory device comes to be more accelerated. In relation with integrating a dynamic random memory (DRAM), which is a semiconductor memory device having general uses, the reduction of cell area and the limitation of charge storage capacity appear as important factors. Accordingly, in order to accomplish the high integration of semiconductor integrated circuit, the unit area of the chip and the cell must be reduced. As a result, it is keenly required that a high level of processing technique be developed, capable of improving the device reliability and securing the charge storage capacity of cell.
In an effort to accomplish the high integration of semiconductor integrated circuit, there have been proposed various methods for fabricating capacitor. A representative conventional method will be, in brief, explained with reference to FIG. 1, for better understanding of the background of the present invention.
To fabricate a DRAM cell shown in the figure, so-called LOCOS (local oxidation of silicon) process is firstly carried cut in a semiconductor substrate 1. As a result, field oxide films 2 are formed on predetermined portions of the semiconductor substrate 1.
A gate oxide film 3 is entirely grown on the resulting structure, followed by the deposition of polysilicon film on the gate oxide film 3.
This polysilicon film is subjected to a photo etching process, to form gate electrodes 4 and word lines 5 and then, impurities are implanted in the semiconductor substrate 1.
Thereafter, the resulting structure is entirely coated with an oxide film which is subsequently subjected to an anisotropic etching process to form spacers 7 at the side walls of the gate electrodes 4 and the word lines 5.
Using the spacers as masks, impurities are implanted in the semiconductor substrate 1 to form an active region (drain region 8 and source region 8') for a lightly doped drain (hereinafter "LDD") structure that is to improve the electric characteristics of MOSFET, based on high integration.
An insulating film 11 is formed at high temperature by use of an oxidation process, followed by the formation of boro-phosphorous-silicate glass (hereinafter "BPSG") film over the insulating film 12. The BPSG film is subjected to the treatment of planarization. As a result, the surface of the resulting structure comes to be substantially plane.
After depositing a first polysilicon film over the resulting structure, the first polysilicon film atop the BPSG film is selectively removed by use of a mask for forming contact holes for bit lines, so as to form mask polysilicon films 13. On carrying out this etching process, the upper portion of the BPSG film is removed together with the first polysilicon film.
Over the resulting structure, there is entirely deposited a second polysilicon film which is subsequently subjected to the treatment of anisotropic etching, so as to form spacers 14 at the side walls of the mask polysilicon film 13 and the BPSG film etched.
Using the spacers as masks, an anisotropic etching process is applied to the remaining BPSG film, to form a contact hole exposing a part of the drain region 8 therethrough. As a result, the contact holes are self-aligned with the spacers 14.
A third polysilicon film implanted with impurities and a silicide film are deposited, in due order, on the drain region 8 through the contact hole, so as to form a polycide which is subsequently to subjected to patterning, to form a bit line 15.
Using a high temperature oxidation process, an insulating oxide film 16 is formed in a predetermined thickness to insulate devices, and then, over the insulating oxide film 16, there is formed a BPSG film 17 in a predetermined thickness, which is subjected to etch for the planarization of the resulting surface.
After depositing a fourth polysilicon film over the entire, plane surface of the BPSG film, the fourth polysilicon film atop the BPSG film 17 is selectively removed by use of a mask for forming contact holes for charge storage electrodes, so as to form mask polysilicon film 27. On carrying out this etching process, the upper portion of the BPSG film is removed and a predetermined thickness of the BPSG film 17 are removed together with the fourth polysilicon film 27.
Over the resulting structure, there is entirely deposited a fifth polysilicon film which is subsequently subjected to the treatment of anisotropic process, so as to form spacers 21 at the side walls provided by the mask polysilicon film 27 and the BPSG film 17 etched.
An anisotropic etching process is applied to the BPSG film 17, to remove the insulating materials stacked on the source region 8', thereby forming contact holes which are to connect charge storage electrodes with the source regions 8'.
Over the resulting structure, there is entirely deposited a sixth polysilicon film implanted with impurities, so that it is connected with the source region 8'. Thereafter, this sixth polysilicon film is subjected to patterning, to form charge storage electrodes 10.
On the entire, exposed surfaces of the charge storage electrodes 10, there is grown a dielectric film 25, such as nitride/oxide (hereinafter "NO") or oxide/nitride/oxide (hereinafter "ONO"), on which a polysilicon implanted with impurities is deposited, so as to form a plate electrode 26.
However, as the semiconductor memory device fabricated by the conventional method is highly integrated, it is difficult secure the electrostatic capacity sufficiently, in consideration of the current working ability. Even though an article with the conventional semiconductor memory device is produced, its quality is low, so that the competitive price power is deteriorated